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n0707hkim vl-2194 no.7202-1/59 LC89057W-VF4A-E 1. overview the LC89057W-VF4A-E is an audio ic th at demodulates and modulates signals according to data transfer format between digital audio devices via the iec60958/61937 and eiaj cp-1201 and supports up to 192khz of sampling frequency. it features a built-in vco and oscillation amplif ier, two bit clock circuits that are capable of setting independently the frequency-dividing ratios that can also be used for the dsp data input/output clocks, and lr clock output pins. a multi-channel pcm interface using multiple LC89057W-VF4A-E ics is also available through a master/slave function. this ic is optimal for use in high performance av am plifiers and a multi-channel pcm interface for dvd audio equipment. 2. features 2.1 realizes full demodulation for high performance av equipment ? possible to receive the sampling frequency of 32khz to 192khz and 24 bits data at a maximum. ? supports i 2 s data output that facilitates interfacing with dsp. ? output clock: 512fs, 256fs, 128fs, 64fs, 32fs, 2fs, fs, and fs/2 ? possible to output oscillation amplifier and exte rnal input clocks regardless of the pll status. ? maintains output clock continuity during clock switching. ? supports multi-channel transfer and r eception, using master/slave function. ? possible to process demodulation functions us ing common low-jitter clock without using pll (external clock synchronization function) ? built-in pll error lock prevention circuit to provide accurate lock ordering number : en7202a cmos ic digital audio interface transceiver specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC89057W-VF4A-E no.7202-2/59 2.2 outputs various information to make system configuration easy ? outputs dts-cd/ld detection flag by dts sync signal detection. ? outputs burst preamble pc fr om microcontroller interface. ? calculates sampling frequency of input signal and outputs it from microcontroller interface. ? outputs interrupt signal for microcontro ller (interrupt source can be selected). ? outputs signal of transitional period switching between vco clock and oscillation amplifier clock. ? outputs bit 1 of channel status (non-pcm data detection bit). ? outputs emphasis information of channel status. ? outputs renewed flag of the first 48 bits channel status. ? channel status bit, validity flag and user data output are selectable. ? outputs modulation/demodulation preamble b information. ? possible to carry out and ou tput various settings through microcontro ller interface. 2.3 plenty of built-in functions to reduce peripheral circuits ? includes modulation function that can attach channel status, validity flag, and user data. ? equipped with a total of 7 digital data input pins: 1 input pin with an amplifier and 6 input pins with 5v tolerable ttl level signal. ? possible to monitor input pin status with microcontroller by mounting a bi-phase input data detection function. ? possible to select input data among 8 system input data including modulation function output. ? possible to select output of input-data through among 8 system input data aside from selecting demodulation data. ? includes 2 system bit clock and lr clock outputs. various frequency-dividing ratios can be set to one of these two systems. ? equipped with a serial digital audio data input pin. possible to switch with demodulation output. ? possible to modulate the data that is input to the serial digital audio data input pin. ? includes built-in oscillation amplifier and frequency divide r for quartz resonator and also possible to use them as clock generator. ? includes 4 bits general-purpose parallel i/o port. it can be used for interface with peripheral ics. ? all the channel status can be decoded through peripheral circuit using preamble b information. ? a continuous switching operation between external clock synchronous mode and pll clock synchronous mode is possible. ? single 3.3v-power supply operation. ttl input port supp orts 5v interface. ? adopts small sqfp48 package for effi cient use of substrate mounting area. package dimensions unit : mm (typ) 3163b sanyo : sqfp48(7x7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (0.75) 112 13 24 25 36 37 48
LC89057W-VF4A-E no.7202-3/59 4. pin assignment 5. pin functions table 5.1 pin functions pin no. name i/o function 1 rxout o output pin of input bi-phase selection data 2 rx0 i 5 input pin of ttl-compatible digital data 3 rx1 i digital data input pin with built-in amplifier that supports coaxial 4 rx2 i 5 input pin of ttl-compatible digital data 5 rx3 i 5 input pin of ttl-compatible digital data 6 dgnd digital gnd 7 dv dd digital power supply 8 rx4 i 5 input pin of ttl-compatible digital data 9 rx5/vi i 5 ttl-compatible digital data || va lidity flag input pin for modulation 10 rx6/ui i 5 ttl-compatible digital data || user data input pin for modulation 11 dv dd digital power supply for pll 12 dgnd digital gnd for pll 13 lpf o pll loop filter connection pin 14 av dd analog power supply for pll 15 agnd analog gnd for pll 16 rmck o r system clock output pin (256fs, 512fs, xin, vco) 17 rbck o/i r system bit clock input/output pin (64fs) 18 dgnd digital gnd 19 dv dd digital power supply 20 rlrck o/i r system lr cl ock input/output pin (fs) 21 rdata o output pin of serial audio data 22 sbck o s system bit clock out put pin (32fs, 64fs, 128fs) 23 slrck o s system lr clock output pin (fs/2, fs, 2fs) 24 sdin i 5 input pin of serial audio data continued on next page. 39 38 37 di rerr slrck sdin do 36 42 41 40 45 44 43 48 47 46 cl ce dgnd xmode tmck/pio0 dv dd tlrck/pio2 tbck/pio1 txo/pioen tdata/pio3 int 35 ckst/pb 34 a udio/vo 33 32 31 lc89057w-vf4 a -e top view dv dd 30 xin 29 empha/uo/cd dgnd 28 27 dv dd 26 dv dd dgnd dgnd 25 x out xmck 23 24 2 1 rdata sbck dv dd rlrck rbck dgnd a gnd rmck lpf a v dd * rx5/vi * rx6/ui * : pull-down resistor internal dv dd * rx4 * rx3 dgnd rx1 * rx2 rxout * rx0 4 3 6 5 8 7 10 9 12 11 21 22 19 20 17 18 15 16 13 14
LC89057W-VF4A-E no.7202-4/59 continued from preceding page. pin no. name i/o function 25 dgnd digital gnd 26 dv dd digital power supply 27 xmck o oscillation amplifier output pin 28 xout o quartz resonat or connection output pin 29 xin i quartz resonator connection , input pin of external supply clock (24.576mhz or 12.288mhz) 30 dv dd digital power supply 31 dgnd digital gnd 32 empha/uo/co i/o emphasis information || u data output || c data output || chip address setting pin 33 audio /vo i/o non-pcm detection || v flag output || chip address setting pin 34 ckst /pb i/o output of clock switch transitional period signal || preamble b output || de modulation master or slave function switch pin 35 int i/o interrupt output for microcontroller (possible to sele ct an interrupt factor.) || modulation or general-purpose i/o switch pin 36 rerr o pll clock error, data error flag output 37 do o microcontroller i/f, read data output pin (3-state) 38 di i 5 microcontroller i/f, write data input pin 39 ce i 5 microcontroller i/f, chip enable input pin 40 cl i 5 microcontroller i/f, clock input pin 41 xmode i 5 system reset input pin 42 dgnd digital gnd 43 dv dd digital power supply 44 tmck/pio0 i/o 256fs or 128fs sy stem clock input for modulation || 256fs or 512fs system clock input for external clock sync function || general-purpose i/o pin 45 tbck/pio1 i/o 64fs bit clock input for modulation || general-purpose i/o pin 46 tlrck/pio2 i/o fs clock input for modulation || general-purpose i/o pin 47 tdata/pio3 i/o serial audio data input for modulation || general-purpose i/o pin 48 txo/pioen o/i modulation data output || general-purpose i/o enable input pin 1) withstand voltage input/output: i or o = -0.3 to 3.6v, i 5 = -0.3 to 5.5v 2) pins 32 and 33 are input pins for chip address setting, when pin 41 = "l". 3) pin 34 is a demodulation functio n master or an input pin for sl ave setting, when pin 41 = "l". 4) pin 35 is a modulation function or an input pin for general-purpose i/o func tion switch setting, when pin 41 = "l". 5) on/off for all power supplies must be done at the same timing as a latch-up countermeasure.
LC89057W-VF4A-E no.7202-5/59 6. block diagram 7. comparison between lc89057w-vf4 and lc89057w-vf4a table 7.1 difference between lc89057w-vf4 and lc89057w-vf4a item lc89057w-vf4 lc89057w-vf4a dir function: external synchronization mode 256fs clock input 256fs or 512fs clock input dir function: setting of rerr wait time after pll is locked after preamble b is counted 6. after preamble b is counted 12. after preamble b is counted 24. after preamble b is counted 48. after preamble b is counted 3. after preamble b is counted 6. after preamble b is counted 12. after preamble b is counted 24. dir function: setting of clock wait time after pll is unlocked 50 s from when oscillation amplifier starts 100 s from when oscillation amplifier starts 200 s from when oscillation amplifier starts 400 s from when oscillation amplifier starts 0 s from when oscillation amplifier starts 50 s from when oscillation amplifier starts 100 s from when oscillation amplifier starts 200 s from when oscillation amplifier starts dir function: channel status bit output microcontroller re ad out microcontroller read out or terminal output (full decode processing possible) dir function: preamble b info output { dit function: system clock 256fs clock input 256fs or 128fs clock input dit function: preamble b info output { 32 33 35 48 39 38 41 cbit, ubit microcontroller i/f 37 empha/uo/co audio /vo int cl ce ci xmode demodulation & lock detect data selector 21 36 do rerr rdata pll clock selector input selector 2 3 4 5 8 9 10 13 modulation or parallel port rx0 rx1 rx2 rx3 rx4 rx5/vi rx6/ui lpf 44 tmck/pio0 45 tbck/pio1 46 tlrck/pio2 47 tdata/pio3 48 txo/pioen 24 sdin 16 rmck 17 rbck 20 rlrck 22 sbck 23 slrck 1/n 27 1 rxout 29 28 34 xin xout xmck ckst /pb
LC89057W-VF4A-E no.7202-6/59 8. electrical characteristics 8.1 absolute maximum ratings table 8.1: absolute maximum ratings at agnd = dgnd = 0v parameter symbol conditions ratings unit maximum supply voltage av dd max 8-1-1 -0.3 to +4.6 v maximum supply voltage dv dd max 8-1-2 -0.3 to +4.6 v input voltage 1 v in 1 8-1-3 -0.3 to +3.9 v input voltage 2 v in 2 8-1-4 -0.3 to +5.8 v output voltage v out 8-1-5 -0.3 to +3.9 v storage ambient temperature tstg -55 to +125 c operating ambient temperature topr -30 to +70 c maximum input/output current i in , i out 8-1-6 20 ma 8-1-1: av dd pin 8-1-2: dv dd pin 8-1-3: rx1, rbck, rlrck, xin, tmck/pio0, tbck /pio1, tlrck/pio2, tdata/pio3, txo/pioen pins 8-1-4: rx0, rx2, rx3, rx4, rx5/vi, rx6/ui, sdin, di, ce, cl, xmode pins 8-1-5: rxout, rmck, rbck, rlrck, sbck, slrck, rdata, xmck, xout, empha/uo/co, _________ audio/vo pins, ________ ckst /pb, _____ int, rerr, do, tmck/pio0, tbck /pio1, tlrck/pio2, tdata/pio3, txo/pioen pins 8-1-6: per input/output pin 8.2 allowable operating ranges table 8.2: allowable operating ranges at ta = -30 to 70 c, agnd = dgnd = 0v ratings parameter symbol conditions min typ max unit supply voltage av dd , dv dd 3.0 3.3 3.6 v input voltage range 1 v in 1 8-2-1 0 3.3 3.6 v input voltage range 2 v in 2 8-2-2 0 3.3 5.5 v operating temperature topr -30 70 c 8-2-1: rx1, rbck, rlrck, xin, tmck/pio0, tbck /pio1, tlrck/pio2, tdata/pio3, txo/pioen pins 8-2-2: rx0, rx2, rx3, rx4, rx5/vi, rx6/ui, sdin, di, ce, cl, xmode pins
LC89057W-VF4A-E no.7202-7/59 8.3 dc characteristics table 8.3: dc characteristic s at ta = -30 to 70c, av dd = dv dd = 3.0 to 3.6v, agnd = dgnd = 0v ratings parameter symbol conditions min typ max unit input, high v ih 0.7v dd v input, low v il 8-3-1 0.2v dd v input, high v ih 2.0 5.8 v input, low v il 8-3-2 -0.3 0.8 v output, high v oh v dd -0.8 v output, low v ol 8-3-3 0.4 v output, high v oh v dd -0.8 v output, low v ol 8-3-4 0.4 v output, high v oh v dd -0.8 v output, low v ol 8-3-5 0.4 v output, high v oh v dd -0.8 v output, low v ol 8-3-6 0.4 v input amplitude v pp 8-3-7 200 mv consumption current i dd 1 8-3-8 1.7 3.4 ma consumption current i dd 2 8-3-9 17 34 ma consumption current i dd 3 8-3-10 19 38 ma 8-3-1: cmos compatible: rbck, rlrck, xin input pins 8-3-2: ttl compatible: input pins other than those listed above 8-3-3: i oh = ? 12ma, i ol = 8ma: rmck output pin 8-3-4: i oh = ? 8ma, i ol = 8ma: xmck, xout output pins 8-3-5: i oh = ? 4ma, i ol = 4ma: rxout, rbck, rlrck, rdata, s bck, slrck, tmck/pio 0, tbck/pio1, tlrck/pio2 output pins, tdata/pio3, txo/pioen output pins 8-3-6: i oh = ? 2ma, i ol = 2ma: output pins other than those listed above 8-3-7: before capacitance of rx1 input pin 8-3-8: demodulation function and oscillation amplifier stopped, modulation only, output sampling frequency = 96khz 8-3-9: xin input continuo us 24.576mhz oscillation, demodulation only, input sampling frequency = 96khz 8-3-10: xin input continuou s 24.576mhz oscillation, modulation, i nput/output sampling frequency = 96khz
LC89057W-VF4A-E no.7202-8/59 8.4 ac characteristics table 8.4: ac characteristic s at ta=-30 to 70c, av dd =dv dd =3.0 to 3.6v, agnd=dgnd=0v ratings parameter symbol conditions min typ max unit rx0 to rx6 sampling frequency f rfs 28 195 khz xin clock frequency f xf 1 8-4-1 8 12.288 19 mhz xin clock frequency f xf 2 8-4-2 20 24.576 30 mhz rmck clock frequency f rck 4 100 mhz rmck clock jitter tj 200 ps rmck, rbck delay t mbo 10 ns rbck, rdata delay t bdo 10 ns rmck, sbck delay t mbo 8-4-3 10 ns sbck, rdata delay t bdo 8-4-4 10 ns tmck input pulse width t wmi 10 ns rx*, tmck delay t rdi 1/4tmck ns tbck input pulse width t wbi 40 ns tlrck sampling frequency t tfs 28 195 khz tbck, tdata setup t dsi 20 ns tbck, tdata hold t dhi 20 ns tmck, tbck delay t mbi 8-4-5 10 ns tbck, tdata delay t bdi 10 ns 8-4-1: xinsel = 0 setting, 12.288mhz must be set when calculating input sampling frequency 8-4-2: xinsel =1 setting, 24.576mhz must be set when calculating input sampling frequency 8-4-3: when rmck and sbck source clocks are identical 8-4-4: when sbck is the pll source clock 8-4-5: tcksel = 0 setting (256fs), the fa lling edge of tbck is in synchronization with the rising edge of tmck. tcksel = 1 setting (128fs), the falling edge of tbck is in synchronization with the falling edge of tmck. figure 8.1 ac characteristics t wbi t wbi tbck (i) tdata (i) tlrck (i) t dsi t dhi t bdi tmck (i) rbck (o) rdata (o) rlrck (o) t bdo rmck (o) t mbo t mbi t wmi rx* (i) t rdi
LC89057W-VF4A-E no.7202-9/59 8.5 microcontroller interface ac characteristics table 8.5: i/f ac characteristics at ta=-30 to 70c, av dd =dv dd =3.0 to 3.6v, agnd=dgnd=0v ratings parameter symbol conditions min typ max unit xmode pulse width, low t rst dw 200 s int pulse width, low t int wd 8-5-1 5 1/fs 36 s cl pulse width, low t cl dw 100 ns cl pulse width, high t cl uw 100 ns cl, ce setup time t ce setup 50 ns cl, ce hold time t ce hold 50 ns cl, di setup time t di setup 50 ns cl, di hold time t di hold 50 ns cl, ce hold time t cl hold 50 ns cl, do delay time t cl to do 20 ns ce, do delay time t ce to do 20 ns 8-5-1: when intopf is set to "1", fs = input sampling frequency figure 8.2 microcontroller interface ac characteristics cl di ce do t cldw t cluw t cehold t cesetup t disetup t dihold t cltodo t cetodo t clhold int t intdw hi-z
LC89057W-VF4A-E no.7202-10/59 9. initial system settings 9.1 system reset (xmode) ? the system operates correctly when xmode is set to "h" after 3.0v or higher supply voltage is applied. when xmode is set to "l" after power is turned on, the system is reset. ? when setting chip address, de modulation function master or slave, and modulation functi on or general-purpose i/o function, connect a 10k pull-down or pull-up resistor to empha/uo/co, ____________ audio/vo, __________ ckst/pb, and ______ int pins. ? if empha/uo/co, ____________ audio/vo, __________ ckst/pb, and ______ int are not pulled up or down, their pin state is unstable at the time of input. consequently proper setting cannot be realized. for these pins, pull-up or pull-down resistor must be connected. table 9.1: pin names and settings setting pins chip address empha/uo/co, ________ audio/vo demodulation function master or slave _______ ckst/pb modulation function or general-purpose i/o function ____ int figure 9.1 setting timing chart of function setting input pins dv dd xmode set pin state 3.3v 3.0v setting input state output state normal system operation range setting completed undefined min. 200
LC89057W-VF4A-E no.7202-11/59 9.2 chip address settings (empha/uo/co, ___________ audio/vo) ? the LC89057W-VF4A-E comes with a function to set a unique chip address to allow the use of several lc89057w- vf4a-e on the same microcontroller interface bus. ? in chip address setting, connect a 10k pull-down or pull-up resistor to empha/uo/co and ____________ audio/vo. by this setting, 4 kinds of chip addresses can be set at a maximum. ? chip addresses in the microcontroller interface are set with cal and cau provided as the first two bits on the lsb side. cal corresponds to the lower chip address and cau to the higher chip address. ? command writing is enabled by making the chip address settings with empha/uo/co and ____________ audio/vo identical to the chip addresses sent from the microcontroller. ? the chip address setting is required even when only one lc 89057w-vf4a-e is used in the system. if the chip address is not set, the chip address is undefined and the microcontro ller cannot control the system. when the microcontroller is not used, a chip address-setting pin is input open while xmode is "l". be sure to connect either a pull-down resistor or a pull-up resistor to empha/uo/co and ____________ audio/vo. table 9.2 chip address settings (register connection) _____ audio/vo empha/uo/co cau cal pull-down pull-down 0 0 pull-down pull-up 0 1 pull-up pull-down 1 0 pull-up pull-up 1 1 figure 9.2 setting example of function setting input pin LC89057W-VF4A-E empha/uo/co a udio/vo ckst/pb int connect to different circuits pull-down 10k pull-up 10k chip address setting demodulation function master or slave setting modulation function or general-purpose i/o port switch call=cau=0 master general-purpose i/o function setting contents of above figure
LC89057W-VF4A-E no.7202-12/59 9.3 demodulation function master/slave settings ( _____ ckst/pb) ? a master/slave function that allows multi-channel synchr onized transfer using multiple LC89057W-VF4A-E ics is included. for this setting, connects either a 10k pull-down or a pull-up resistor to __________ ckst/pb. ? set to the master mode normally, when single LC89057W-VF4A-E ic is used. when multiple LC89057W-VF4A-E ics are used, set one of them to the master mode and the others to the slave mode. ? in the multi-channel synchronous transfer mode usin g multiple LC89057W-VF4A-E ics, connect rbck and rlrck (output) on the master side to rbck and rlrck (input) on the slave side. also connect xmck on the master side to xin on the slave side. at this time, the polarity of rbck and rlrck, and the frequency of xin and xmck must be identical. ? if the input data sampling frequency or the phase are different between the master mode and slave mode or if the clock sources differ while the sampling frequencies are not different, some of the output data may get dropped or read twice on the slave side. you can see if these are happening by _______ int and the microcontroller interface. table 9.3 master/slave switching (register connection) _____ ckst/pb mode pull-down master pull-up slave table 9.4 clock pin state pin master mode slave mode rmck output output rbck output input rlrck output input 9.4 switching between modulation function and general-purpose i/o port ( ____ int) ? the modulation function and the general-purpose i/o function share same pins. therefore, these two functions cannot be used simultaneously. ? to switch functions, connect either a 10k pull-down or pull-up resistor to ______ int pin. table 9.5 switching between modulation function and general-purpose i/o port (register connection) ___ int state function pull-down modulation function pull-up general-purpose i/o
LC89057W-VF4A-E no.7202-13/59 10 description of demodulation function ? the demodulation function is set with rxopr. an initial value is set to an operating status. 10.1 clocks 10.1.1 pll (lpf) ? the LC89057W-VF4A-E incorporates a vco (voltage contro lled oscillator) that can be stopped with pllopr and it synchronizes with sampling frequencies from 32khz to 192kh z and with the data with transfer rate from 4mhz to 25mhz. ? the pll lock frequency is selected with pllsel. for systems whose input data sampling frequency is 105khz or lower, the initial setting of 512fs is recommended. since the initial output value of the system clock rmck is set to 1/2 of pllsel, the rmck output is 256fs when a pll clock frequency is 512fs. ? for reception systems whose sampling frequency is higher than 105khz, switch the pll clock frequency to 256fs. if the same initial output setting is ap plied, rmck is 128fs. then set with prsel[ 1:0] when necessary. ? when the pll lock frequency is selected with pllsel after pll is locked, unlock is generated. accordingly, pllsel must be set prior to bi-phase data input. ? lpf is a pin for pll loop filter. connect the following resistance and capacitances re gardless of pllsel settings. clock r0 c0 c1 512fs 256fs 220 0.1 f 0.022 f figure 10.1 loop filter configuration 10.1.2 demodulation function without using pll (tmck) ? the LC89057W-VF4A-E has a function that processes input bi-phase data using an external clock (external clock synchronization function). in normal demodulation processing, the built-in pll generates a clock that is synchronized with data and carries out data processing with the clock. in the LC89057W-VF4A-E, data processing can be also done by providing a clock synchronized with data instead of the pll-generated clock via an independent transmission path. ? to use the external clock synchronization function, set the pll unused demodulation function with exsync, set the 256fs or 512fs clock with pllsel, and set 1/1 of pllsel set frequency with prsel[1:0]. after that input the clock synchronized with input data to tmck. by this settings , the same operation as pll demodulation processing is performed. for example, 512fs clock should be supplied with tmck because the setting of pllsel is at 512fs in case exsync is set on initial condition. in the event of sw itching the setting of tmck clock frequency to 256fs, the setting of pllsel should be at 256fs. ? jitter of input data and clock should be as small as possible. excessive jitter might invite errors in operation of pll. pay attention to the noise of clock transmission path. ? in the external synchronization mode, supply clock with tm ck all the time. without input of clock, system will shut down and be in malfunction. ? in case of using external clock synchronization mode onl y, it is not necessary to connect anything to lpf pin. however, configuring pll loop filter enables to use bo th pll clock synchronization mode and external clock synchronization mode by switching exsync. ? applying the external clock synchronization function can also configure a high-precision clock system using an external pll. lpf r0 c0 c1
LC89057W-VF4A-E no.7202-14/59 10.1.3 oscillation amplifiers (xin, xout, xmck) ? the LC89057W-VF4A-E features a built-in oscillation amplifie r. connecting a quartz resonator, feedback resistor, and load capacitance to xin and xout can configure an osc illation circuit. when connecting a quartz resonator, use one with a fundamental wave. be aware that the load capa citance depends on the quartz resonator characteristics. ? if the built-in oscillation amplifier is not used and oscillation module is used as the clock source instead, connect the output of an external clock supply source to xin. at this time, it is not necessary to connect a feedback resistor between xin and xout. ? supply xin with the 12.288mhz or 24.576mhz-clock set w ith xinsel. if inputting other frequencies to xin, it is necessary to set that the result of change in sampling frequency fs of input data is not reflected to an error flag. by this setting, the operation functions properly. however, since time definition gap occurs in relation to the operation with recommended frequency, the encoding result cannot be used for input fs calculations. in this case, the input fs can be calculated by dividing decimally the calculation count value with 1/2000th of the xin input frequency. for details, see chapter 12. microcontroller interface. ? since the xin clock serves as the reference for internal processing, complete the xinsel setting prior to bi-phase data input. ? supply xin with clocks all the time to be used in the following applications. (1) detection whether or not bi-phase data is input (2) clock source while pll is unlocked (3) calculation of input data sampling frequency (4) time definition when switching input data (5) external source of supply clock (clock fo r an ad converter, etc.) in xin source mode. ? the oscillation amplifier automatically stops while pll is lock ed. however, it can be also set for continuous operation with ampopr[1:0]. in the continuous operation mode, data detection and calculation of input sampling frequency become possible while the pll is locked. in that case, both the oscillator amplifier clock and the pll clock signals coexist, and then users must pay attention and make sure sound quality is not adversely affected. ? if the oscillation amplifier is set to continuous opera tion with ampopr[1:0] while pll is locked, rerr temporarily outputs an error ("h"). when oscillation amplifier is switche d to an operation state, fs calculation value maintained during a stop state is reset at the same time. this process is regarded as an error, since fs seems to change. this error has no influence on clock output, but rdata is muted during this error period. therefore, setting of the ampopr[1:0] must be completed either prior to bi-phase data input or while pll is unlocked. ? the oscillation amplifier can be stopped if it is unnecessary. however, when the normal operation is resumed, it must wait for 10ms or longer until the resonator oscillation gets stable. ? xmck outputs the xin clock. the xmck output is set with xmsel[1:0]. the xin clock can be set to 1/1, 1/2, or muted output. ? when only the modulation function is used, no clock needs to be supplied to xin. in this case, the built-in oscillation amplifier and frequency divider can be also used for mck, bck, and lrck clock generation. if you use only the oscillation amplifier, input the quartz resonator to xin and xout or an external clock to xin, and fix the electric potential of digital data input pins of rx0 to rx6. at this time, do not set to stop the dir function with rxopr and pllopr. the output clock may be muted.
LC89057W-VF4A-E no.7202-15/59 10.1.4 switching between master clock and clock source ? the rmck, rbck, and rlrck (hereunder, r system), and the sbck and slrck (hereunder, s system) clock sources can be selected among the following three master clocks. (1) pll source (256fs or 512fs) (2) xin source (12.288mhz or 24.576mhz) (3) tmck source (256fs or 512fs) ? there are two ways available for clock source switching; one is to set with the r system and the s system interlocked, and the other is to set only the r system while xin source is fixed in the s system. this setting is carried out with selmtd, ocksel, and rcksel. ? the clock source is automatically switched between pll clock and xin clock by locking/unlocking the pll. during this period, continuity of the clock is maintained. however, if the clock source is switched with selmtd, continuity of the s system is not maintained. ? the clock source can be switched to xin with ocksel and rcksel, regardless of the pll status. the clock source switch command and each clock output of the r and s systems are shown below. table 10.1 correspondence between clock source switch commands and clock output pins selmtd r system output cloc k s system output clock 0 according to ocksel according to ocksel 1 according to rcksel fixed to xin source table 10.2 relationship between clock source switch commands and clock sources when pll locked/unlocked r system clock source s system clock source selmtd ocksel rcksel locked unlocked locked unlocked 0 x pll xin pll xin 0 1 x xin xi n xin xin x 0 pll xin xin xin 1 x 1 xin xi n xin xin ? tmck source should be selected with exysnc and the input clock frequency (256fs or 512fs) should be set with pllsel. the same action as the one of pll source should be taken except inputting clock from tmck on this setting. ? when data synchronized with the tmck source is input, various clocks are output with the tmck source as the master clock, in a manner similar to the pll clock status. in this case as well, the source is switched to xin with ocksel and rcksel. when the tmck source is not supplied or the input data is not synchronized, the source is switched to the xin source, in a manner similar to the pll source unlocked status. ? the pll status can be always monitored with rerr even after switching to the xin source. moreover, the processed information can be read with the microcontro ller interface regardless of the pll status. ? when the pll changes from the locked status to the unlocked, the timing for switching the clock from the pll source to the xin source can be changed with xtwt [1:0]. use these commands if noise occurs during clock switching.
LC89057W-VF4A-E no.7202-16/59 10.1.5 points to notice about switching clock source while pll is locked ? in the state where the pll is lock ed, if the clock is switched to xin source with selmtd, ocksel, and rcksel while the oscillator amplifier is stopped (initial setting), cl ock continuity is maintained but rerr temporarily outputs an error (high level) indication. when switched to xin s ource, the oscillator amplifier is switched to the operating state at the same time. consequently the input fs calculation restarts. at this time, the previous fs calculation value is reset and compared with the newly calculated fs value. then those two values are found not identical, that?s why the error is temporarily issued. ? the following settings are required to switch the cl ock source with selmtd, ocksel, and rcksel without changing the rerr status while pll is locked. (1) set the oscillation amplifier to the continuous operation mode with ampopr[1:0]. (2) set with fserr to the mode where fs change is not reflected to the error flag. ? by one of the above settings, changing of the rerr status can be constrained when the clock source is switched with selmtd, ocksel, and rcksel. ? when switching the clock source to xin from the state where the oscillation amplifier is stopped while the pll is locked, the output clock using xin as the source starts being output after the oscillation amplifier starts operating. when the pll is locked, switching of the clock source from xin to pll is performed instantaneously. in either case, clock continuity is maintained. 10.1.6 master clock block diagram (tmck, xin, xout, rmck, xmck) ? the relationships between the three master clocks, switching, and the frequency division function, are described below. ? the contents in the square brackets [ ??? ] by the switch and function blocks correspond to the write command names. ? lock/unlock is automatically switched by pll locking/unlocking. figure 10.2 master clock block diagram pll 1/n (256fs or 512fs) selected biphase tmck (i) 256fs or 512fs xin (i) xout (o) rmck (o) xmck (o) [exsync] [rcksel] [pllopr] [pllsel] [prsel1] [xrsel1] [xinsel] [xmsel1] [ampopr1] (n=1, 2) lock /unlock 1/n (n=1, 2) 1/n (n=1, 2, 4) 1/n (n=1, 2, 4) [ocksel] [xmsel0] [xrsel0] [prsel0] [selmtd] [ampopr0]
LC89057W-VF4A-E no.7202-17/59 10.1.7 output clocks (rmck, rbck, rlrck, sbck, slrck) ? the LC89057W-VF4A-E features two clock systems (r and s systems) in order to supply the various needed clocks to peripheral devices such as a/d converter and dsp. ? the clock output settings for the r and s systems are done with prsel[1:0], xrsel[1:0], xrbck[1:0], xrlrck[1:0], psbck[1:0], pslrck[1:0], xsbck[1:0], and xslrck[1:0]. ? setting range for each clock output pin when the pll is used as source (1) rmck: selection from 1/1, 1/2, and 1/4 of 512fs or 256fs (2) rbck: 64fs output (3) rlrck: fs output (4) sbck: selection from 128fs, 64fs, and 32fs (5)slrck: selection from 2fs, fs, and fs/2 ? setting range for each clock output pins when the xin is used as source (1) rmck: selection from 1/1, 1/2, and 1/4 of 12.288mhz or 24.576mhz (2) rbck: selection from 12.288mhz, 6.144mhz, and 3.072mhz (3) sbck: selection from 12.288mhz, 6.144mhz, and 3.072mhz (4) rlrck: selection from 192khz, 96khz, and 48khz (5) slrck: selection from 192khz, 96khz, and 48khz ? setting range for each clock output pins when the tmck is used as source (1) rmck: selection from 1/1, 1/2,1/4 of 512fs or 256fs. (2) rbck: 64fs output (3) rlrck: fs output (4) sbck: selection from 128fs, 64fs, 32fs (5) slrck: selection from 2fs, fs, fs/2 ? the polarity of rbck, rlrck, sbck, and slrck can be reversed with rbckp, rlrck p, sbckp, and slrckp. ? clock switching is processed from the rising edge of rlrc k output after the falling edge of microcontroller interface ce. table 10.3 list of output clock frequencies (bold items = initial settings) pll source (internal vco ck) tmck source (tmck input ck) xin source (xin input ck) output pin name 512fs 256fs 512fs 256fs 12.288mhz 24.576mhz rmck 512fs 256fs 128fs 256fs 128fs 64fs 512fs 256fs 128fs 256fs 128fs 64fs 12.288mhz 6.144mhz 3.072mhz 24.576mhz 12.288mhz 6.144mhz rbck 64fs 12.288mhz 6.144mhz 3.072mhz rlrck fs 192khz 96khz 48khz sbck 128fs 64fs 32fs 12.288mhz 6.144mhz 3.072mhz slrck 2fs fs fs/2 192khz 96khz 48khz
LC89057W-VF4A-E no.7202-18/59 10.1.8 output clocks block diagram (rm ck, rbck, rlrck, sbck, slrck, xmck) ? the relationships between the output clock and switch function are shown below. ? pll in the figure indicates the pll sour ce (or tmck source), and xin the xin source. ? the contents in the square brackets [ ??? ] by the switch function blocks correspond to the write command names. ? the broken lines connecting the switches indicate coordinated switching. ? lock/unlock is switched automatically by pll locking/unlocking. ? master/slave is switched by master/slave function switching of demodulation function. figure 10.3 clock output block diagram master clock generator sbck (o) slrck (o) xmck (o) xtal source pll source rmck (o) 512fs / 256fs 256fs / 128fs 128fs / 64fs mute 2fs fs fs/2 mute rbck (i/o) rlrck (i/o) to internal circuits pll 64fs pll fs [rcksel] ([selmtd]=1) master / slave 128fs 64fs 32fs mute 12.288mhz / 24.576mhz 6.144mhz / 12.288mhz mute lock / unlock [prsel] [xrsel] [psbck] [pslrck] [xslrck] [xmsel] [selmtd] 12.288mhz / 24.576mhz 6.144mhz / 12.288mhz 3.072mhz / 6.144mhz mute [xrbck] [xrlrck] 12.288mhz 6.144mhz 3.072mhz mute [xsbck] 192khz 96khz 48khz mute pll xin pll xin pll xin pll xin pll xin xin 192khz 96khz 48khz mute 12.288mhz 6.144mhz 3.072mhz mute 12.288mhz or 24.576mhz 256fs or 512fs tmck source 256fs or 512fs [ocksel] ([selmtd]=0)
LC89057W-VF4A-E no.7202-19/59 10.1.9 output of clock switch transition signal ( ____________ ckst ) ? __________ ckst outputs "l" pulse when the output clock changes by pll lock/unlock. ? in the lock-in stage, the __________ ckst "l" pulse falls at the word clock genera ted from the xin clock after pll is locked following detection of input data, and rises at the same timing as rerr after a designated period. ? in the unlock stage, the __________ ckst "l" pulse falls at the same timing as re rr, pll lock detection signal, and rises after word clocks generated from the xin clock are counted for a designated period. ? change of the pll lock status and timing of the clock change can be seen by detecting the rising and falling edges of the __________ ckst "l" pulse. figure 10.4 clock switch timing rx0 to rx6 pll status xtal clock vco clock ckst rerr rmck (a): lock-in stage digital data unlock lock after pll lock 45ms to 300ms same timing as rerr digital data unlock unlock 0.6ms to 6.4ms same timing as rerr rx0 to rx6 pll status xtal clock vco clock ckst rerr rmck (b): unlock stage
LC89057W-VF4A-E no.7202-20/59 10.2 bi-phase signal i/o 10.2.1 reception range of bi-phase signal input ? reception range of the input data depends on the pll lo ck frequency setting done w ith pllsel. the relationship between this setting and the guaranteed reception range is shown below. table 10.4 relationship between pll output clock setting and reception range (fslim [1:0] = 00) pll output clock setting input data reception range 512fs (pllsel = 0) 28khz to 105khz 256fs (pllsel = 1) 28khz to 195khz ? the fs reception range for input data can be limited within the set range of pll output clocks stated above. this setting is carried out with fslim [1:0]. when this func tion is adopted, input data exceeding the set range is considered as an error, the clock so urce is automatically switched to the xi n source, and rdata output data is subject to the rdtsel setting. 10.2.2 bi-phase signal i/o pins (rx0 to rx6, rxout) ? there are 7 kinds of digital data input pins. moreover, data modulated with the modulation function is also available and thus there are 8 options in total. however, the pins to be selected are restricted, depending on the setting conditions. (1) the six pins of rx0 and rx2 to rx6 are ttl level input pins with 5v-tolerance voltage. (2) rx1 is an input pin with built-in amplifier, which is coaxial-compatible and it, can receive up to min, 200mvp-p data. ? the demodulation input and rxout output signals could each be selected independently. (1) the demodulation data is selected with risel [2:0]. (2) the rxout output data is selected with rosel [2:0]. ? rxout can be muted with rxoff. muting is recomme nded to reduce clock jitter when rxout is not used. ? the data input status can be monitored with the rxmon se tting. the status of each data input pin is stored in ccb address 0xea and output registers do0 to do7. since this function uses the xin clock, the oscillation amplifier must be set to the continuous operation mode when rxmon is set. ? demodulation input pin can be switched via pll unlock with the ulsel setting. thus data switching can be accurately conveyed to peripheral devices. the interval from pin switching through risel [2:0] until the data is received is about 250 s to 350 s. in this function, the oscillation amplifier also needs to be set to the continuous operation mode. figure 10.5 input pin selecting process via pll unlock input pin selection rx0 rx2 rx3 rx1 rx0 rx2 rx3 rx1 internal supply signal 250
LC89057W-VF4A-E no.7202-21/59 10.2.3 bi-phase signal input circuits (rx0, rx1, rx2) ? if rx1 with a built-in amplifier is used as a coaxial in put pin, malfunction may occur due to the influence from the adjacent rx0 and rx2 input pins. to avoid the influences from those pins, fix rx0 and rx2 to "l". ? when rx1 is selected and the input signal to rx1 is temporarily open because of ac coupling, the rx0 and rx2 potential must be fixed. in this case, there are 5 bi-phase signal input pins available, which are rx1 and rx3 to rx 6. ? when rx1 is selected and the input signal to rx1 is alwa ys fixed to either "h" or "l", rx0 and rx2 processes are not required. in this case, all 7 input pins can be used validly. figure 10.6 bi-phase signal input circuits (b):optical input circuit (a):coaxial input circuit coaxial optical LC89057W-VF4A-E 0.1 100 optical optical LC89057W-VF4A-E etc. etc. rx0 rx1 rx2 rx3 rx4 rx5 rx6 rx0 rx1 rx2 rx3 rx4 rx5 rx6
LC89057W-VF4A-E no.7202-22/59 10.3 serial audio data i/o 10.3.1 output data format (rdata) ? the output format is set with ofsel [2:0]. ? the initial value of output format is i 2 s. ? right-adjusted output is valid only in the master mode. in the slave mode, data is not output correctly. ? output data is output synchronized with the rlrck edge immediately after the rerr output becomes "l". figure 10.7 data output timing (0): i 2 s data output (1): msb-first front-loading data output (2): msb-first back-loading data output msb lsb msb lsb lsb 16, 20, 24bit 16, 20, 24bit l-ch r-ch msb lsb msb lsb max. 24bit max. 24bit l-ch r-ch msb msb lsb msb lsb max. 24bit max. 24bit l-ch r-ch rlrck (o) rbck (o) rdata (o) rlrck (o) rbck (o) rdata (o) rlrck (o) rbck (o) rdata (o)
LC89057W-VF4A-E no.7202-23/59 10.3.2 serial audio data input format (sdin) ? serial digital audio data input pin of sdin capable of 24 bits input is provided. ? the format of the serial audio data input to sdin and the demodulation data output format must be identical. the initial value of modulation data output is i 2 s. figure 10.8 serial audio data input timing (0): i 2 s data input (1): msb-first front-loading data input (2): msb-first back-loading data input 16, 20, 24bit 16, 20, 24bit msb lsb msb lsb l-ch r-ch msb msb lsb msb lsb l-ch r-ch rlrck (o) rbck (o) rdata (o) rlrck (o) rbck (o) rdata (o) msb lsb msb lsb max. 24bit max. 24bit sdin (i) msb lsb msb lsb max. 24bit max. 24bit msb sdin (i) l-ch r-ch rlrck (o) rbck (o) rdata (o) msb lsb msb lsb lsb sdin (i) msb lsb msb lsb lsb
LC89057W-VF4A-E no.7202-24/59 10.3.3 output data switching (sdin, rdata) ? rdata outputs demodulation data when the pll is locked, and outputs sdin input data when the pll is unlocked. this output is automatically switched according to the pll locked/unlocked status. for details, see the timing charts below. ? when sdin input data is selected, switch to a clock source synchronized to the sdin data. ? with the rdtsta setting, the sdin input data is output to rdata regardless of the locked/unlocked status of the pll. ? with the rdtmut setting, the rdata output data can be also muted forcibly. ? even when the clock source is set to xin with ocksel and rcksel, the pll continues operating as long as the pll is not stopped with pllopr. at this time, the pll st atus is continuously output from rerr unless error output is forcibly set with resta. moreover, the processed in formation can be read with the microcontr oller interface regardless of the pll status. figure 10.9 timing chart of rdata output data switching pll status ckst rerr (a): lock-in stage unlock lock (b): unlock stage sdin data muted demodulation data pll status rdata ckst rerr lock unlock sdin data muted demodulation data rdata
LC89057W-VF4A-E no.7202-25/59 10.3.4 data block diagram (rx0 to rx 6, tx0, rxout, tdata, rdata, sdin) ? the rdata output data can be switched to sdin input data with rdtsel. ? the sdin input data can be input to the modulation function with tdtsel. ? since the modulation output is input to the input switc h multiplexer, it can be fetched from rxout. using this function, it is possible to use a signal digitized with the a/d converter for digital recording output, etc. figure 10.10 data system diagram 10.3.5 calculation of input data sampling frequency ? the input data sampling frequency is calculated using the xin clock. ? in the mode where the oscillation amplifier automatically stops according to the lock status of the pll, the input data sampling frequency is calculated during the rerr error peri od and completed when the oscillation amplifier stops with holding the value. therefore, the value remains unchanged until the pll becomes unlocked. ? if the oscillation amplifier is in a continuous operation mode, calculation is repeated constantly. even if sampling changes within the pll capture range for input data whose channel status sampling information does not change, the calculation results that follow the input data can be read. ? the calculation result can be read from ccb address 0xeb and output registers do4 to do7 and do8 to do15. registers do4 through do7 hold the encoded result, while do8 through do15 hold the calculated counter value. however, as the calculation count value is output in 8 bit un its, fs capable of being calcula ted are greater than 24khz. for details, see chapter 12. microcontroller interface. rx0 mux (8in / 2out) dir rx1 rx2 dit rx3 rx4 rx5 rx6 tdata sdin rdata rxout txo [tdtsel] [rdtsel]
LC89057W-VF4A-E no.7202-26/59 10.4 error output processing 10.4.1 lock error and data error output (rerr) ? rerr outputs an error flag when a pl l lock error or a data error occurs. ? it is possible to treat non-pcm data reception as an error by the resel setting. ? the rerr output conditions are set with resta. since the pl l status can be output at all times, the pll status can be always monitored, even when the clock source is xin. 10.4.2 pll lock error ? the pll gets unlocked for input data that lost bi-phase mo dulation regularity, or input data for which preambles b, m, and w cannot be detected. ? rerr turns to "h" upon occurrence of a pll lock error, and returns to "l" when data demodulation returns to normal and "h" is maintained for some where between 45ms and 300ms. ? the rising and falling edges of rerr are synchronized with rlrck. 10.4.3 input data parity error ? odd number of errors among parity bits in input data and input parity errors are detected. ? if an input parity error occurs 9 or more times in succe ssion, rerr turns to "h" indicating that the pll is locked, and after holding "h" for somewhere between 45ms and 300ms, it returns to "l". ? the error flag output format can be se lected with reder, when an input parity error is output less than 9 times in succession. 10.4.4 other errors ? even if rerr turns to "l", the channel status bits of 24 to 27 (sampling frequency) are al ways fetched and the data of the previous block is compared with the current data. mo reover, the input data sampling frequency is calculated from the fs clock extracted from the input data, and the fs calculate d value is compared in a same way as described above. if any difference is detected in these data, rerr is instantly ma de "h" and the same processing as for pll lock errors is carried out. ? the pll causes a lock error when the fs changes as desc ribed above. however, in order to support sources with a variable fs (for example a cd player with a variable pitc h function), it is possible to set with fserr not to output an error flag unless fs changes exceeding the pll capture range. moreover, in the fserr setting, when the pll is locked, re rr is turned to ?l? without reflecting the fs calculation result to the error flag concerning input da ta within reception range by fslim[1:0]. ? if a setting which regard non-pcm data input as an error is made with resel, rerr turns to ?h? when non-pcm data input is detected. at this time, the pll locked status and various output clocks are subject to the input data, but the output data is muted.
LC89057W-VF4A-E no.7202-27/59 10.4.5 data processing upon occurrence of errors (lock error, parity error) ? the data processing upon occurrence of an error is described below. if 8 or fewer input parity errors occur in succession and transfer data is pcm audio data, the data is replaced by the one saved each in l-ch and r-ch in the previous frame. however, if the transfer data is non-pcm da ta, the error data is output as it is. non-pcm data is the data of when bit 1 non-pcm data detection bit of the channel status turns to "h" based on the data detected prior to the occurrence of the i nput parity error. ? output data is muted when a pll lock error occurs or a parity error occurs 9 or more times in succession. ? as for the channel status output, the data of the previous block is held in 1-bit units when a parity error occur 8 or fewer times in succession. table 10.5 data processi ng upon error occurrence data pll lock error input parity error (a) input parity error (b) input parity error (c) rdata output ?l? ?l? previous value data output fs calculation result ?l? output output output channel status ?l? ?l? previous value data previous value data validity flag ?l? ?l? output output user data ?l? ?l? output output * input parity error (a): if occu rs 9 or more times in succession * input parity error (b): if occurs 8 or fe wer times in succession, in case of audio data * input parity error (c): if occurs 8 or fewer times in succession, in case of non-pcm burst data ? figure 10.11 shows an example of data pro cessing upon occurrence of a parity error. figure 10.11 example of data processing upon parity error occurrence l-1 r-1 l-2 r-2 l-3 r-3 l-4 r-4 l-5 r-5 l-6 r-6 l-7 r-7 l-8 r-8 input data 1occurrence rerr rlrck l-0 r-0 l-1 r - 0 l-2 r-2 l - 2 r - 2 l - 2 r - 2 l - 2 r - 2 l - 2 rdata r-ch l-ch r-ch 9 times or mote : muting previous value data previous value data
LC89057W-VF4A-E no.7202-28/59 10.4.6 processing during error recovery ? when preambles b, m, and w are detected, pll becomes locked and data demodulation begins. ? rdata output data is output from th e rlrck edge after rerr turns to "l". figure 10.12 data processing when data demodulation starts 10.5 channel status data output 10.5.1 data delimiter bit 1 output ( ________ audio ) ? ____________ audio outputs bit 1 of the channel status that indicates whether the input bi-phase data is pcm audio data. ____________ audio is immediately output upon detection of rerr even during "h" output period. ? or-output with iec61937 or with the dts-cd/l d detection flag is also possible with aosel. table 10.6 ____________ audio output ______ audio output conditions l pcm audio data (cs bit 1 = "l") h non-audio data (cs bit 1 = "h") 10.5.2 emphasis inform ation output (empha) ? empha outputs shows wh ether there are 50/15 s emphasis parameters for consumer and broadcast studio. empha is immediately output upon detection of rerr even during "h" output. table 10.7 empha output empha output conditions l no pre-emphasis h 50/15 s pre-emphasis rerr 45ms to 300ms ok rdata rlrck data output start from rlrck edge immediately after rerr flag is lowered internal lock signal
LC89057W-VF4A-E no.7202-29/59 10.6 other outputs 10.6.1. validity flag output (vo) ? the validity flag can be output from ____________ audio/vo by switching the contents of ____________ audio/vo output by vosel. ? the validity flags transferred in units of each sub-frame are output in the following timing. ? the validity flag is generated 0.5 to 1 frame earlier than the output data in error. table 10.8 vo output vo output conditions l no error (not burst data) h error (may be burst data) figure 10.13 validity flag output timing 10.6.2 user data output (uo) ? user data can be output from empha/uo/co by switching the contents of empha/uo/co output by uosel. ? the uossel setting, however, is enabled only when pesel1 is se t to 0; it is disabled if pbsel1 is set to 1. the state of pbsel0 has nothing to do with this processing ? the user data transferred in units of each sub-frame are output in the following timing. figure 10.14 user data output timing rlrck rbck vo rlrck rbck uo u uuuu
LC89057W-VF4A-E no.7202-30/59 10.6.3 channel status data output (co) ? possible to output channel status data from empha/uo/co by switching pbsel1 that performs the setting of preamble b synchronization signal output. ? polarity of rlrck is uncertain because channel status da ta loads data and outputs them on each sub-flame. however, the timing for a period of h output of preamble b synchronization signal pb and bit 0 data output (c0 lch, c0 rch) of channel status is shown on the following figure. figure 10.15 channel status data output timing 10.6.4 preamble b synchronization signal output (pb) ? possible to output preambles b synchronization signal that is block synchronization of channel status from __________ ckst/pb by switching the content of __________ ckst/pb output by pbsel [1:0]. ? for the period that bit 0 data of the channel status is output, pb signal outputs h. for the otherwise period, it outputs l. ? regarding pbsel [1:0], possible to output preamble b synchronization signal with dit function. however, impossible to set output preamble b with dir function and dit function from pb at once because they share the terminal. ? in case of setting preamble b synchronization signal output with dir function, the channel status data is output from empha/uo/co pin, and the setting of uosel is invalid. rlrck rbck co c0 lch c0 rch c1 lch c1 rch c2 lch pb
LC89057W-VF4A-E no.7202-31/59 10.7 iec61937, dts-cd/ld detection flag output ? a function to output iec61937 and dts-cd/ld detection flags for non-pcm data is provided. ? when the unpcm of non-pcm signal output setting is selected through the ______ int output contents setting, an interrupt signal is output from ______ int detecting an iec61937 or dts-cd/ld sync signal. reading output register from this information can see details of non-pcm signal. ? when bit 1 of channel status is non-pcm data ("1"), the iec61937 sync signal is detected and output. if bit 1 is pcm data, the iec61937 sync signal is not output. ? dts-cd/ld sync signal detection is done based on the sync pattern and the base frequency. dts-es data detection is output when the dts5.1 channel sync signal is detected and the dts-es sync pattern is verified. ? the iec61937 and dts-cd/ld detection flags are cleared wh en fs have changed or a pll lock error or data error has occurred. ? since the dts sync signal is provided within the audio data , digital data with the same code as the dts sync signal may exist in rare cases for regular cd/l d records that are not recorded in th e dts format. protection using the sync pattern or base frequency is provided so that such data is not misinterpreted as dts-cd/ld detection flags. the detection sequence is shown below. figure 10.16 iec61937 and dts-cd/ld data detection sequence papb detection during 4096 frames frame count 512,1024,2048,4096 sync detection no yes yes no yes no yes no no yes papb detection input data dts-cd/ld sync detection * * * depending on the frame count, the subsequent detection count is expanded up to 2. periodic fluctuation is supported. 512 ? 512 or 1024 1024 ? 1024 or 2048 2048 ? 2048 or 4096 4096 ? 4096 1st count 2nd count dts-cd/ld data hold iec61937 flag ok int lowered frame counter start yes no no yes bit 1detection bit 1=1 iec61937 data hold frame counter reset frame counter start frame counter reset iec61937 flag not valid int lowered dts-cd/ld flag ok int lowered dts-cd/ld flag not valid int lowered frame count hold x2 count detection expansion papb detection during 4096 frames frame count 512,1024,2048,4096 sync detection
LC89057W-VF4A-E no.7202-32/59 11. description of modulation func tion and general-purpose i/os 11.1 how to use modulation function 11.1.1 initial setting ? the modulation function and general-purp ose i/o port function cannot be used si multaneously because they share the same pins. to select the modulation function, pull down ______ int with a 10k resistor. for further information about the setting, see chapter 9. ? in the initial setting, the modulation function is stopped. to apply the modulation fu nction, set it with txopr. 11.1.2 data output (tmck, tbck, tlrck, tdata, txo) ? output bi-phase modulated data from txo by inputting 256fs or 128fs clock into tmck, 64fs clock into tbck, fs clock into tlrck, audio data into tdata. ? set tcksel for clock frequency to input into tmck. howeve r, the falling edge of tbck is in synchronization with the rising edge for tmck when the tmck is set at 256fs. also, the falling edge of tmck is in synchronization with the falling edge of tbck when tmck is set at 128fs. ? the polarity of the tlrck clock is set with txlrp. ? input data can be modulated in the sampling range of 32khz to 192khz, in the transfer rate of 4mhz to 25mhz, and up to 24-bit data. ? the initial value for the input data format is set in i 2 s. switching to msb-first right-ad justed input is set with txdfs. ? for the channel status, the first 48 bits of data can be written with the microcontroller interface. ? txo is fixed to "l" by setting txopr to stop or txmut. figure 11.1 data input timing (0): i 2 s data output (1): msb-first front-loading data output msb lsb msb lsb max. 24bit max. 24bit l-ch r-ch msb msb lsb msb lsb max. 24bit max. 24bit l-ch r-ch tlrck (i) tbck (i) tdata (i) tlrck (i) tbck (i) tdata (i)
LC89057W-VF4A-E no.7202-33/59 11.1.3 validity flag input (vi) ? validity flags can be input from rx5/vi by switching the contents of rx5/vi input by visel. ? the timing of writing a validity flag is shown below. the validity flag can be also written with the microcontroller interface, but port settings have priority over the validity flag. ? writing validity flags with the microcon troller interface is done using vmode. table 11.1 rx5/v1 input rx5/vi output conditions 0 no error 1 error figure 11.2 validity flag input timing 11.1.4 user data input (ui) ? user data can be input from rx6/ui by switching the contents of rx6/ui input by uisel. ? the timing of writing the user data is shown below. ? it is also possible to write user data using the preamble b sync signal as the referenc e. generation of the preamble b sync signal is configured in pbsel[1:0] as in the case of the dir function. after the setting, the signal is output from ckst/pb. figure 11.3 user data input timing v-l2 v-r2 v-l3 v-r1 v-l1 l1 l2 l3 r2 r1 tlrck tbck vi internal latch signal internal latch signal tlrck tbck ui u u u u u
LC89057W-VF4A-E no.7202-34/59 11.1.5 modulated output of sdin input data ? sdin input data is modulated and its output can be fetched from txo and rxout. ? to modulate sdin input data, set it with tdtsel. ? input a clock synchronized with sdin to tmck, tbck, and tlrck. ? the sdin input data format must be identical to the setting used during modulation processing. 11.1.6 monaural output ? it is possible to output only single channel data of the inpu t data at half the rate of the input fs with txmod[1:0]. ? this operation maintains the bi-phase modulation regul arity, but there is no correlation between the data and preambles. ? channel status write is synchronized with the output rate. ? the validity flag and user data are written in units of frame. input the same data to the l and r channels. ? to process the stereo signals of two channels with this setting, two units of LC89057W-VF4A-E are required. figure 11.4 data modulation of single channel 11.2 general-purpose i/os (pio0, pio1, pio2, pio3 pioen) 11.2.1 initial settings ? the modulation function and general-purpose parallel i/os share the same pins and therefore they cannot be used simultaneously. to use the general-purpose i/os, pull up ______ int with a 10k resistor. for further information about the setting, see chapter 9. ? the general-purpose parallel i/o applies parallel-conversion to the serial data input from the microcontroller interface, and outputs it from pio0, pio1, pio2, and pio3. the input fu nction saves the parallel data input to pio0, pio1, pio2, and pio3 in internal registers and reads the contents of these registers with th e microcontroller interface. ? 4-bit general-purpose i/os cannot be used with both input and output mixed. switching between input and output is done with pioen. when pioen is "h", all the general-purpose i/os become input pins. when pioen is "l", all the general-purpose i/os become output pins. 11.2.2 i/o settings ? data handling for general-pu rpose i/os is done using the microcontro ller interface and write/read registers. see chapter 12 microcontroller interface for details. ? general-purpose i/o writes settings (microcontroller write register general-purpose i/o output) (1) to output data from general-purpose i/os, set pioen to "l". (2) set the data to be output to ccb address 0xe8, co mmand address 0x10, and input registers di12 to di15. (3) during write operation, be sure to input "0 " to di8 to di11 of modulation setting registers. (4) the data written to pi0 to pi3 is output from the general-purpose i/os. ? general-purpose i/o read setti ngs (general-purpose i/o input read register microcontroller) (1) to input data to general-purpose i/os, set pioen to "h". (2) the input data is saved in ccb address 0xeb and output registers do0 to do3. (3) data can be sent to the microcontroller by reading po0 to po3. tlrck tdata txo [1] l2 l3 l4 l1 l0 txo [2] r2 r3 r4 r1 r0 l1 r1 l2 r2 l3 r3 l4 r4 l5 r5 r0 m w m w m w m w m m ln rn
LC89057W-VF4A-E no.7202-35/59 12. microcontroller interface ( _____ int , cl, ce, di, do) 12.1 description of microcontroller interface 12.1.1 interrupt output ( ____ int) ? interrupts are output when a change has occurred in the pll lock status or output data information. ? interrupt output consists of the register for selecting the interrupt source, the ______ int pin that outputs that state transition, and the registers that store the interrupt source data. ? normally ______ int outputs "l" upon occurrence of an interrupt while "h " is output. following "l" output, it returns to "h" according to the intopf setting. ? intopf determines whether to hold the "l" pulse for a certain period and then clear it ("h"), or to clear it at a time when the output register is read. ? the interrupt sources can be selected among the following items. mu ltiple sources can be selected at the same time with the contents of ccb address 0xe8 and command address 0x08. ______ int outputs or calculation result of the selected interrupt sources. ______ int output = (selected source 1) + (selected source 2) + ... + (selected source n) table 12.1 interrupt source setting contents no. command name description 1 error output when rerr pin status has changed 2 indet output when input data pin status has changed (subj ect to oscillation amplifier operation condition) 3 fschg output when input fs calculation result has changed. (subject to oscillation amplifier condition) 4 csrnw output when channel status data of first 48 bits have updated 5 unpcm output when ______ audio pin status has changed 6 pcrnw output when burst preamble pc has been updated 7 slipo output when data is read twice during slave setting and missing data is detected 8 empf output when emphasis information has changed ? the contents of set interrupt source are saved in outp ut registers do8 to do15 of ccb address 0xea, when the source occurs. however, for the read registers for source items 1 and 5, the each status of the rerr and ____________ audio pins are output at the time of reading. other data except for so urce items 1 and 5 are saved in the registers upon occurrence of an interrupt source. ? concerning source items 2 and 3, the oscillation amplifier cl ock is used. therefore, if the status is monitored even while the pll is locked, the oscillation amplifier must be set to the continuous operation mode. ? clearing ______ int at the same time of readout of an output register is carried out immediately after the output register 0xea is set. ? the pulse width of the setting in which the ______ int output following the occurrence of an interrupt source is set to the "l" pulse output mode is somewhere between 1/2fs and 3/2fs for one interrupt source. 12.1.2 ccb format ? the various function settings as well as information wr iting and reading are performed with the microcontroller interface. ? the data format of the micr ocontroller interface conforms to sanyo's origin al serial bus format (ccb), but three-state is employed instead of open-drain for the data output format. ? data input/output is performed following ccb address input. for the data input/output timing, see the input/output timing chart. table 12.2 relationship between regi ster i/o contents and ccb addresses register i/o contents r/w ccb address b0 b1 b2 b3 a0 a1 a2 a3 function setting data input write 0xe8 0 0 0 1 0 1 1 1 cs data input write 0xe9 1 0 0 1 0 1 1 1 interrupt data output read 0xea 0 1 0 1 0 1 1 1 fs data output read 0xeb 1 1 0 1 0 1 1 1 cs data output read 0xec 0 0 1 1 0 1 1 1 pc data output read 0xed 1 0 1 1 0 1 1 1
LC89057W-VF4A-E no.7202-36/59 12.1.3 data write procedure ? input is performed in the following sequence: ccb addresses of a0 to a3 and b0 to b3, chip addresses of di0 and di1, command addresses of di4 to di7, and data of di8 to di15. di2 and di3 are reserved for the system. input must be doing "0". ? for the chip addresses, di0 corresponds to cal (low-order), and di1 to cau (high-order). for details, see section 9.2. 12.1.4 data read procedure ? read data is output from do. do is in the high impedance state when ce is "l", and begins outputting from the rising edge of ce after output setting is established at the ccb addr ess. do then returns to the high impedance state at the falling edge of ce. ? if do outputs are shared using multiple lc89057w-vf4 a-e units, it is possible to set the do outputs of the LC89057W-VF4A-E units of which data is not to be read to be always in the high impedance state with doen. with this setting, only the targeted outputs can be read. 12.1.5 i/o timing figure 12.1 input timing chart (normal l clock) figure 12.2 input timing chart (normal h clock) figure 12.3 output timing chart (normal l clock) figure 12.4 output timing chart (normal h clock, do0 need be read with port) di1 di2 di3 di4 di5 di15 ce cl do b1 b0 b2 b3 a0 a1 a2 a3 di0 di hi-z di1 di2 di3 di4 di5 di15 ce cl do b1 b0 b2 b3 a0 a1 a2 a3 di0 di hi-z do1 do2 do3 do4 don ce cl do b1 b0 b2 b3 a0 a1 a2 a3 do0 di hi-z do1 do2 do3 do4 don ce cl do b1 b0 b2 b3 a0 a1 a2 a3 do0 di hi-z
LC89057W-VF4A-E no.7202-37/59 12.2 write data 12.2.1 list of write commands ? a list of the write commands is shown below. ? to write the commands shown in the following table, set the ccb address to 0xe8. table 12.3 write register map add. setting items di15 di 14 di13 di12 di11 di10 di9 di8 0 all system setting testm 0 txopr rxopr intopf 0 doen sysrst 1 demodulation system setting pbsel1 pbsel0 fslim1 fslim0 rxmon aosel vosel uosel 2 master clock ampopr1 ampopr0 exsync pllopr xmsel1 xmsel0 xinsel pllsel 3 r system output clock xrlrck1 xrlrck0 xrbck1 xrbck0 xrsel1 xrsel0 prsel1 prsel0 4 s system output clock xslrck1 xslrck0 xsbck1 xsbck0 pslrck1 pslrck0 psbck1 psbck0 5 source switch 0 rdtmut rdtsta rdtsel 0 rcksel ocksel selmtd 6 data input/output rxoff rosel2 ro sel1 rosel0 ulsel risel2 risel1 risel0 7 output format setting slrckp sbc kp rlrckp rbckp 0 ofsel2 ofsel1 ofsel0 8 ___ intsource selection empf slipo p crnw unpcm csrnw fs chg indet error 9 rerr condition setting erwt1 erwt0 fserr resta xtwt1 xtwt0 reder resel 10 modulation system setting p13 p12 p11 p10 0 vmode visel uisel 11 modulation data setting tcksel 0 tx mod1 txmod0 txmut tdtsel twlrp txdfs 12 test 0 0 0 0 0 0 0 0 13 test 0 0 0 0 0 0 0 0 14 test 0 0 0 0 0 0 0 0 15 test 0 0 0 0 0 0 0 0 ? the shaded parts of di8 to di15 in the command area are reserved bits. input must be doing "0". ? command addresses 0x12 to 0x15 are reserved for testing purposes. writing to these addresses is prohibited.
LC89057W-VF4A-E no.7202-38/59 12.2.2 details of write commands ccb address: 0xe8; command address: 0; all system settings di7 di6 di5 di4 di3 di2 di1 di0 0 0 0 0 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 testm 0 txopr rxopr intopf 0 doen sysrst sysrst system reset 0: don't reset (initial value) 1: reset circuits other than command registers doen do pin output setting 0: output (initial value) 1: always high impedance state (read disabled) intopf ______ int pin output setting 0: output "l" level during source occurrence (initial value) 1: output "l" pulse during source occurrence rxopr setting of demodulation operation 0: operate (initial value) 1: stop txopr setting of modulation operation 0: stop (initial value) 1: operate testm test mode setting 0: normal operation (initial value) 1: enter test mode ? when reset by sysrst is done or the demodulation is se t to stop with rxopr, rbck and sbck output "l", and rlrck and slrck output "h".
LC89057W-VF4A-E no.7202-39/59 ccb address: 0xe8; command address: 1; demodulation function: system setting di7 di6 di5 di4 di3 di2 di1 di0 0 0 0 1 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 pbsel1 pbsel0 fslim1 fslim0 rxmon aosel vosel uosel uosel empha/uo/co pin setting (when pbsel1 is set to 0.) 0: empha emphasis output (initial value) 1: uo user data output vosel ____________ audio/vo pin setting 0: ____________ audio channel status bit 1 output (initial value) 1: vo validity flag output aosel output contents at the time of setting ____________ audio is set with ____________ audio/vo pin 0: only output channel status bit 1 (initial value) 1: output channel status bit 1, iec61937 or dts-cd/ld detection flag rxmon setting of digital data input status monitoring 0: don't monitor data input status (initial value) 1: monitor data input status fslim [1:0] setting of sampling frequency r eception range for input digital data signal 00: no limit (initial value) 01: fs 96khz 10: fs 48khz 11: reserved pbsel [1:0] __________ ckst/pb pin setting 00: signal output of switching transition term of __________ ckst clock (initial value) 01: preamble b synchronization signal output with pb, dit function 10: preamble b synchronization signal output with pb, dir function 11: reserved ? in case of setting with pbsel at 1, terminal of empha/ uo/co will be channel status data output terminal co and the setting for uosel is impossible. in case of setting w ith pbsel at 0, the setting for empha/uo/co terminal follows the setting for uosel. ? the setting of aosel comes into effect in the case that the b it 1 output of channel status is selected with vosel. in the case that 1 is selected with aosel, ____________ audio / vo terminal output high level, when either channel status bit 1 or iec61937, non-pcm synchronous signal is detected.
LC89057W-VF4A-E no.7202-40/59 ccb address: 0xe8; command address: 2; de modulation function: master clock setting di7 di6 di5 di4 di3 di2 di1 di0 0 0 1 0 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 ampopr1 ampopr0 exsync pllopr xmsel1 xmsel0 xinsel pllsel pllsel pll lock frequency setting 0: 512fs (fs 96khz commend) (initial value) 1: 256fs xinsel xin input frequency setting 0: 12.288mhz (initial value) 1: 24.576mhz xmsel [1:0] xmck output frequency setting 00: 1/1 of xin input frequency (initial value) 01: 1/2 of xin input frequency 10: reserved 11: muted pllopr pll (vco) operation setting 0: operate (initial value) 1: stop exsync setting of pll unused demodulation (external synchronization) 0: pll used normal operation (initial value) 1: pll unused external synchronization operation (supply 256fs clock to tmck) ampopr [1:0] oscillation amplifier operation setting 00: automatic stopping of oscillation amplifier while pll is locked (initial value) 01: permanent continuous operation 10: reserved 11: stop ? if the pll is stopped with pllopr wh ile the pll is locked, the output clocks are all muted and this muted status continues even if the pll is unlocked. ? if the permanent continuous operation is set with ampopr[1 :0] while the pll is locked, rerr goes to into the error status once. it is possible to set the operation with ma intaining the rerr status, if a setting with which even a changed fs is not regarded as an error du e to the pll status is made with fserr. ? when an automatic stop mode of the oscillation amplifier is set with ampopr[1:0], and if the input fs changes within the pll capture range and no lock error occurs, fs is not calculated with the oscillation amplifier stopped. for this reason, the input data fs and the fs calculation result ma y not be identical. however, if the channel status fs information is rewritten in line with input data changes, this information is reflected to the error flag and fs calculation of the input data is carried out. since the fs calculation is always done when the oscillation amplifier is set to the permanent continuous operation mode, fs cha nges are always reflected to the error flag.
LC89057W-VF4A-E no.7202-41/59 ccb address: 0xe8; command address: 3; demodul ation function: r syst em output clock setting di7 di6 di5 di4 di3 di2 di1 di0 0 0 1 1 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 xrlrck1 xrlrck0 xrbck1 xrbck0 xrsel1 xrsel0 prsel1 prsel0 prsel [1:0] setting of rmck output frequency while pll is locked 00: 1/2 of pllsel setting frequency (initial value) 01: 1/1 of pllsel setting frequency 10: 1/4 of pllsel setting frequency 11: muted xrsel [1:0] setting of rmck output frequency during xin source 00: 1/1 of xinsel setting frequency (initial value) 01: 1/2 of xinsel setting frequency 10: 1/4 of xinsel setting frequency 11: muted xrbck [1:0] setting of rbck output frequency during xin source 00: 3.072mhz output (initial value) 01: 6.144mhz output 10: 12.288mhz output 11: muted xrlrck [1:0] setting of rlrck output frequency during xin source 00: 48khz output (initial value) 01: 96khz output 10: 192khz output 11: muted ? if the rmck frequency is set lower than rbck when th e xin source is used, 3.072mhz is output from rbck. this also applies to sbck.
LC89057W-VF4A-E no.7202-42/59 ccb address: 0xe8; command address: 4; demodul ation function: s syst em output clock setting di7 di6 di5 di4 di3 di2 di1 di0 0 1 0 0 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 xslrck1 xslrck0 xsbck1 xsbck0 pslrck1 pslrck0 psbck1 psbck0 psbck [1:0] setting of sbck frequency while pll is locked 00: 64fs output (initial value) 01: 128fs output 10: 32fs output 11: muted pslrck [1:0] setting of slrck frequency while pll is locked 00: fs output (initial value) 01: 2fs output 10: fs/2 output 11: muted xsbck [1:0] setting of sbck frequency during xin source 00: 3.072mhz output (initial value) 01: 6.144mhz output 10: 12.288mhz output 11: muted xslrck [1:0] slrck output frequency setting during xin source 00: 48khz output (initial value) 01: 96khz output 10: 192khz output 11: muted
LC89057W-VF4A-E no.7202-43/59 ccb address: 0xe8; command address: 5; demodula tion function: clock sour ce; rdata output setting di7 di6 di5 di4 di3 di2 di1 di0 0 1 0 1 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 0 rdtmut rdtsta rdtsel 0 rcksel ocksel selmtd selmtd setting of output clock source switching method 0: switch r system and s system simultaneously according to ocksel (initial value) 1: switch r system according to rck sel and fix s system to xin source ocksel clock source setting when selmtd = 0 0: use xin clock as source while pll is unlocked (initial value) 1: use xin clock as source regardless of pll status rcksel clock source setting when selmtd = 1 0: use xin clock as source while pll is unlocked (initial value) 1: use xin clock as source regardless of pll status rdtsel rdata output setting while pll is unlocked 0: output sdin data while pll is unlocked (initial value) 1. mute while pll is unlocked rdtsta rdata output setting 0: according to rdtsel (initial value) 1: output sdin input data regardless of pll status rdtmut rdata mute setting 0: output data selected with rdtsel 1: muted ? when the oscillation amplifier is set to the permanent co ntinuous operation mode with ampopr[1:0] or fs changes are set not to be reflected to the error flag with fse rr, ocksel and rcksel can switch the clock source while maintaining the rerr status. however, if none of these settings is made, rerr outputs an error once when switching occurs. ? to input data to sdin, select a clock synchronized with the sdin input data. ? the xin source can be switched while maintaining the pll locked status. however, since switching between clock and data output can be set independently, it is recommended to select mute or sdin data for the output data when xin source is switched. ? if the oscillation amplifier is set to stop automatically when the pll gets locked, xin source switching from the pll locked status is executed after the oscillation is stabilized. mo reover, switching of output data at this time is subject to xin source switching.
LC89057W-VF4A-E no.7202-44/59 ccb address: 0xe8; command address: 6; demodulatio n function: digital data input/output port setting di7 di6 di5 di4 di3 di2 di1 di0 0 1 1 0 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 rxoff rosel2 rosel1 rosel0 ulsel risel2 risel1 risel0 risel [2:0] data demodulation input pin setting 000: rx0 selection (initial value) 001: rx1 selection 010: rx2 selection 011: rx3 selection 100: rx4 selection (however, vi input is performed when visel is set.) 101: rx5 selection (however, ui input is performed when uisel is set.) 110: rx6 selection 111: modulation function output (txo output data) selection ulsel setting of input pin via pll unlock 0: normal setting (initial value) 1: setting of input data switching via pll unlock rosel [2:0] rxout output data setting 000: rx0 input data (initial value) 001: rx1 input data 010: rx2 input data 011: rx3 input data 100: rx4 input data 101: rx5/vi input data 110: rx6/ui input data 111: modulation function output (txo output data) selection rxoff setting of rxout output status 0: rosel[2:0] selection data output (initial value) 1: "l" fixed output ? ulsel can be set when the oscillation amplifier is set to the permanent continuous operation mode with ampopr[1:0]. ulsel does not work correctly when the oscillation amplifier is stopped.
LC89057W-VF4A-E no.7202-45/59 ccb address; 0xe8; command address: 7; demodul ation function: output data format setting di7 di6 di5 di4 di3 di2 di1 di0 0 1 1 1 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 slrckp sbckp rlrckp rbckp 0 ofsel2 ofsel1 ofsel0 ofsel [2:0] audio data output format setting 000: i 2 s data output (initial value) 001: msb-first left-justification data output 010: 24 bits msb-first right-justification data output (master mode only) 011: 20 bits msb-first right-justification data output (master mode only) 100: 16 bits msb-first right-justification data output (master mode only) 101: reserved 110: reserved 111: reserved rbckp rbck output polarity setting 0: falling rdata data change (initial value) 1: rising rdata data change rlrckp rlrck output polarity setting 0: "l" period: l-channel data; "h" period: r-channel data (initial value) 1: "l" period: r-channel data; "h" period: l-channel data sbckp sbck output polarity setting 0: falling rdata data change (initial value) 1: rising rdata data change slrckp slrck output polarity setting 0: "l" period: l-channel data; "h" period: r-channel data (initial value) 1: "l" period: r-channel data; "h" period: l-channel data ? the data output format and rlrck output polarity could be set independently. set the rlrch polarity in line with each data output format.
LC89057W-VF4A-E no.7202-46/59 ccb address: 0xe8; command addre ss: 8; demodulation function: ______ int output contents setting di7 di6 di5 di4 di3 di2 di1 di0 1 0 0 0 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 empf slipo pcrnw unpcm cs rnw fschg indet error error rerr signal output setting 0: don't output (initial value) 1: output rerr pin status change indet input data detection output setting 0: don't output (initial value) 1: output input data pin status change fschg setting of updated flag output of pll lock frequency calculation result 0: don't output (initial value) 1: output updated flag of pll lock frequency calculation result csrnw output setting for updated flag of first 48-bit channel status data 0: don't output (initial value) 1: output update flag of first 48-bit channel status data unpcm output setting for change flag of non-pcm data detection 0: don't output (initial value) 1: output ____________ audio pin status change pcrnw output setting for updated flag of burst preamble pc 0: don't output (initial value) 1: output updated flag of burst preamble pc slipo output setting of slip signal during slave operation 0: don't output (initial value) 1: output duplicate reading and a detection flag for missing of data output empf output setting of emphasis detection flag 0: don't output (initial value) 1: output emphasis detection flag ? the channel status update flag compares the first 48 bits of data of the previous block with those of the current block. if these data are identical, it outputs a flag , considering the data has been updated. ? the burst preamble pc update flag also compares the 16 bits of data of the pr evious block with those of the current data. if they are identical, an update flag is output.
LC89057W-VF4A-E no.7202-47/59 ccb address: 0xe8, command address: 9; de modulation function: rerr output setting di7 di6 di5 di4 di3 di2 di1 di0 1 0 0 1 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 erwt1 erwt0 fserr resta xtwt1 xtwt0 reder resel resel rerr output contents setting 0: pll lock error or data error (initial value) 1: pll lock error or data error or non-pcm data reder setting of parity error flag output within 8 times in a row 0: output only when non-pcm data is recognized (initial value) 1: output only during sub-frame for which error was generated xtwt [1:0] setting of clock switch wait time after pll is unlocked 00: clock switching after approx. 200 s from when oscillation amplifier starts (initial value) 01: clock switching after approx. 100 s from when oscillation amplifier starts 10: clock switching after approx. 50 s from when oscillation amplifier starts 11: clock switching after pll is unlocked resta rerr output condition setting 0: output pll status all the time (output pll status even during xin source) (initial status) 1: forcibly output error (set "h" to rerr forcibly) fserr setting of error flag output condition according to fs change 0: reflect fs changes to error flag (initial value) 1: don't reflect fs changes to error flag erwt [1:0] setting of rerr wait time after pll is locked 00: cancel error after preambl e b is counted 3 (initial value) 01: cancel error after preamble b is counted 24 10: cancel error after preamble b is counted 12 11: cancel error after preamble b is counted 6 ? for non-pcm data, the data defined with aosel is reflected. in other words, it is identical to the detected data output to ____________ audio. ? output data is muted if an error oc curs due to non-pcm data with resel. ? the resta setting is not reflected to the output pins of data and clock. ? for fserr, the fs calculation result obtained while the oscillati on amplifier is stopped is not reflected. in this case, fs changes consist of only cha nnel status fs information. ? erwt[1:0] defines the interval of time for rerr to outp ut error cancellation ("l") after pll is locked. since demodulated audio data is output after re rr cancels an error, you need to change this setting if the situation that the head of data is missing is a problem.
LC89057W-VF4A-E no.7202-48/59 ccb address: 0xe8; command address: 10; modulation function: system setting, general-purpose i/o data input di7 di6 di5 di4 di3 di2 di1 di0 1 0 1 0 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 pi3 pi2 pi1 pi0 0 vmode visel uisel uisel rx6/ui pin setting 0: input rx6 demodulation function data (initial value) 1: input ui modulation function user data visel rx5/vi pin setting 0: input rx5 demodulation function data (initial value) 1: input vi modulation function validity flag vmode modulation function v flag setting 0: write 0 (initial value) 1: write 1 pi0 data input when general-purpose i/o pio0 output is set 0: output l (initial value) 1: output h pi1 data input when general-purpose i/o pio1 output is set 0: output l (initial value) 1: output h pi2 data input when general-purpose i/o pio2 output is set 0: output l (initial value) 1: output h pi3 data input when general-purpose i/o pio3 output is set 0: output l (initial value) 1: output h ? when you use general-purpose i/o pio0 to pio3 as output, set pioen to "l".
LC89057W-VF4A-E no.7202-49/59 ccb address: 0xe8; command address: 11; modulation function: digital audio input/output setting di7 di6 di5 di4 di3 di2 di1 di0 1 0 1 1 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 tcksel 0 txmod1 txmod0 txmut tdtsel txlrp txdfs txdfs tdata input data format setting 0: i 2 s data input (initial value) 1: msb-first left-justification data input txlrp setting of tlrck input clock polarity 0: "l" period: l-channel data; "h" period: r-channel data (initial value) 1: "l" period: r-channel data; "h" period: l-channel data tdtsel input data setting 0: tdata input data (initial value) 1: sdin input data txmut txo output setting 0: modulation data output (initial value) 1: "l" fixed output txmod [1:0] mode setting 00: normal operation (l-channel, r-channel stereo mode) (initial value) 01: l-channel continuity (time-division mode) 10: r-channel continuity (time-division mode) 11: reserved tcksel tmck input clock frequency setting 0: 256fs (initial value) 1: 128fs ? in case of inputting 256fs clock into tmck, the falling edge of tbck should be in synchronized with the rising edge of tmck. also, in case of inputting 128fs clock into tmck , the falling edge of tbck is in synchronized with the falling of tmck.
LC89057W-VF4A-E no.7202-50/59 12.2.3 channel status data write ? for channel status data write with the modulation function, set the ccb address to 0xe9. ? di0 to di7 are not channel status bits. be sure to input a chip address to di0 and di1. input "0" to di2, di3, and di7 because they are reserved by the system. write length of the channel status data is determined with di4 to di6. this setting is possible up to 48 bits in units of 8 bits. ? after ce rises, input a clock combined di0 to di7 and write data length to cl clock to make ce ?l?. for example, if you write data up to the bit 15 by di4 to di6, cl must be 24 clocks while ce is rising. if this setting goes wrong, correct writing is not expected. ? input data is written from preamble b where ce has become "l". table 12.3 relation between setting register of input data length and data length di6 di5 di4 feasible data ra nge for input di6 di5 di4 f easible data range for input 0 0 0 bit 0 to bit 7 1 0 0 bit 0 to bit 39 0 0 1 bit 0 to bit 15 1 0 1 bit 0 to bit 47 0 1 0 bit 0 to bit 23 1 1 0 reserved 0 1 1 bit 0 to bit 31 1 1 1 reserved table 12.4 input setting -setting of modulation function channel status data- (ccb address : 0xe9) register bit no. description register bit no. description di0 cal lower chip address di28 bit 20 channel number di1 cau higher chip address di29 bit 21 di2 0 reserved di30 bit 22 di3 0 di31 bit 23 di4 0 data length setting di32 bit 24 sampling frequency di5 0 di33 bit 25 di6 0 di34 bit 26 di7 0 reserved di35 bit 27 di8 bit 0 application di36 bit 28 clock accuracy di9 bit 1 control di37 bit 29 di10 bit 2 di38 bit 30 not defined di11 bit 3 di39 bit 31 di12 bit 4 di40 bit 32 word length di13 bit 5 di41 bit 33 di14 bit 6 not defined di42 bit 34 di15 bit 7 di43 bit 35 di16 bit 8 category code di44 bit 36 not defined di17 bit 9 di45 bit 37 di18 bit 10 di46 bit 38 di19 bit 11 di47 bit 39 di20 bit 12 di48 bit 40 di21 bit 13 di49 bit 41 di22 bit 14 di50 bit 42 di23 bit 15 di51 bit 43 di24 bit 16 source number di52 bit 44 di25 bit 17 di53 bit 45 di26 bit 18 di54 bit 46 di27 bit 19 di55 bit 47
LC89057W-VF4A-E no.7202-51/59 12.3 read data 12.3.1 list of read commands ? it is possible to read the following items. ? monitor output of digital data input status ? interrupt data output ? output of general-purpose i/o input data ? output of fs calculation result and fs counter data (8 bits) ? output of first 48 bits of channel status ? output of burst preamble pc data ? ccb address 0xeb and output registers do16 to do23 are for testing. table 12.5 read register map read register name 0xea 0xeb 0xec 0xed do0 rxdet0 po0 cs bit 0 pc bit 0 do1 rxdet1 po1 cs bit 1 pc bit 1 do2 rxdet2 po2 cs bit 2 pc bit 2 do3 rxdet3 po3 cs bit 3 pc bit 3 do4 rxdet4 fsc0 cs bit 4 pc bit 4 do5 rxdet5 fsc1 cs bit 5 pc bit 5 do6 rxdet6 fsc2 cs bit 6 pc bit 6 do7 rxdet7 fsc3 cs bit 7 pc bit 7 do8 oerror fsdat0 cs bit 8 pc bit 8 do9 oindet fsdat1 cs bit 9 pc bit 9 do10 ofschg fsdat2 cs bit 10 pc bit 10 do11 ocsrnw fsdat3 cs bit 11 pc bit 11 do12 ounpcm fsdat4 cs bit 12 pc bit 12 do13 opcrnw fsdat5 cs bit 13 pc bit 13 do14 oslipo fsdat6 cs bit 14 pc bit 14 do15 oempf fsdat7 cs bit 15 pc bit 15 do16 csbiti test0 cs bit 16 ? do17 iec1937 test1 cs bit 17 ? do18 dts51 test2 cs bit 18 ? do19 dtses test3 cs bit 19 ? do20 f0512 tset4 cs bit 20 ? do21 f1024 test5 cs bit 21 ? do22 f2048 test6 cs bit 22 ? do23 f4096 test7 cs bit 23 ? do24 ? ? cs bit 24 ? ? ? ? do46 ? ? cs bit 46 ? do47 ? ? cs bit 47 ?
LC89057W-VF4A-E no.7202-52/59 12.3.2 read register 1 (input detection, interrupt flag, iec61937 flag, dts-cd flag) ccb address: 0xea, contents of read register output do7 do6 do5 do4 do3 do2 do1 do0 rxdet7 rxdet6 rxdet5 rxdet4 rxdet3 rxdet2 rxdet1 rxdet0 rxdet0 rx0 input detection 0: no input data in rx0 1: input data exist in rx0 rxdet1 rx1 input detection 0: no input data in rx1 1: input data exist in rx1 rxdet2 rx2 input detection 0: no input data in rx2 1: input data exist in rx2 rxdet3 rx3 input detection 0: no input data in rx3 1: input data exist in rx3 rxdet4 rx4 input detection 0: no input data in rx4 1: input data exist in rx4 rxdet5 rx5 input detection 0: no input data in rx5 1: input data exist in rx5 rxdet6 rx6 input detection 0: no input data in rx6 1: input data exist in rx6 rxdet7 data detection of modulation function output txo 0: no data in modulation function output txo 1: data exist in modulation function output txo ? for readout of rxdet[7:0], rxmon must be set to "h" beforehand.
LC89057W-VF4A-E no.7202-53/59 ccb address; 0xea; contents of read register output do15 do14 do13 do12 do11 do10 do9 do8 oempf oslipo opcrnw ounpcm ocsrnw ofschg oindet oerror oerror rerr output (output status during readout) 0: no transfer erro r while pll is locked 1: transfer error exist or pll is unlocked oindet status change of data input pin (clear after readout) 0: no change in status of data input pin 1: change exists in status of data input pin ofschg result of updating input fs calculation (clear after readout) 0: no update of input fs calculation 1: input fs calculation is updated ocsrnw update result of first 48 bits channel status (clear after readout) 0: not updated 1: updated ounpcm ____________ audio output (output of status during readout) 0: non-pcm signal not detected 1: non-pcm signal detected opcrnw update result of burst preamble pc (clear after readout) 0: not updated 1: updated oslipo detection of duplicate reading and missing data during slave operation (clear after readout) 0: not detected 1: duplicate reading and missing data detected oempf channel status emphasis detection (output of status during readout) 0: no pre-emphasis 1: 50/15 s pre-emphasis exists ? concerning oerror and ounpcm, the status of rerr and ____________ audio that are subject to resel and aosel setting are read regardless of the _______ intoutput setting.
LC89057W-VF4A-E no.7202-54/59 ccb address: 0xea; contents of read register output do23 do22 do21 do20 do19 do18 do17 do16 f4096 f2048 f1024 f0512 dtses dts51 iec1937 csbit1 csbit1 channel status bit 1 detection 0: pcm 1: non-pcm iec1937 iec61937 burst preamble detection 0: pa, pb not detected 1: pa, pb detected dts51 dts-cd/ld 5.1 channel sync signal detection 0: dts-cd/ld sync signal not detected 1: dts-cd/ld sync signal detected dtses dts es-cd/ld 6.1 channel sync signal detection 0: dts es-cd/ld sync signal not detected 1: dts es-cd/ld sync signal detected f0512 dts-cd/ld iec60958 frame interval 0: sync signal is not 512 nor 1024 frame interval 1: sync signal is 512 or 1024 frame interval f1024 dts-cd/ld iec60958 frame interval 0: sync signal is not 1024 nor 2048 frame interval 1: sync signal is 1024 or 2048 frame interval f2048 dts-cd/ld iec60958 frame interval 0: sync signal is not 2048 nor 4096 frame interval 1: sync signal is 2048 or 4096 frame interval f4096 dts-cd/ld iec60958 frame interval 0: sync signal is not 4096 frame interval 1: sync signal is 4096 frame interval
LC89057W-VF4A-E no.7202-55/59 12.3.3 read register 2 (contents of general-purpose i/o input, fs calculation result, fs counter data) ccb address: 0xeb, contents of read register output do7 do6 do5 do4 do3 do2 do1 do0 fsc3 fsc2 fsc1 fsc0 po3 po2 po1 po0 po0 contents of read data output when general-purpose i/o po0 input is set 0: pio0 input = "l" 1: pio0 input = "h" po1 contents of read data output when general-purpose i/o pio1 input is set 0: pio1 input = "l" 1: pio1 input = "h" po2 contents of read data output when general-purpose i/o pio2 input is set 0: pio2 input = "l" 1: pio2 input = "h" po3 contents of read data output when general-purpose i/o pio3 input is set 0: pio3 input = "l" 1: pio3 input = "h" fsc [3:0] input data fs calculation result "xxxx": see code table. table 12.6 code table of input fs calculation result (ta = 25c, av dd = dv dd = 3.3 v) fsc3 fsc2 fsc1 fsc0 target frequen cy calculation range (design value) 0 0 0 0 out of range ? 0 0 0 1 ? ? 0 0 1 0 ? ? 0 0 1 1 ? ? 0 1 0 0 16khz 15.4k to 16.6khz 0 1 0 1 22.05khz 21.2k to 22.9khz 0 1 1 0 24khz 23.1k to 24.9khz 0 1 1 1 32khz 30.8k to 33.3khz 1 0 0 0 44.1khz 42.4k to 45.8khz 1 0 0 1 48khz 46.2k to 49.9khz 1 0 1 0 64khz 61.5k to 66.7khz 1 0 1 1 88.2khz 85.4k to 91.7khz 1 1 0 0 96khz 93.1k to 100.7khz 1 1 0 1 128khz 122.9k to 133.5khz 1 1 1 0 176.4khz 170.7k to 180.7khz 1 1 1 1 192khz 186.2k to 198.1khz
LC89057W-VF4A-E no.7202-56/59 ccb address: 0xeb; contents of read register output do15 do14 do13 do12 do11 do10 do9 do8 fsdat7 fsdat6 fsdat5 fsdat4 fsdat3 fsda t2 fsdat1 fsdat0 fsdat [7:0] fs counter data output ? fsdat [7:0] is the fs calculation counter value. the data length is 8 bits, fsdat0 is lsb, and fsdat7 is msb. ? the relation between the count value and fs is expressed by the following equation. fs = 6144/fsdat (khz) ? since fs is calculated with 6.144mhz-clock, th e calculation accuracy is subject to this clock. ? the calculation counter value is 8-bit output, so the fs capable of calculating is 24khz or higher. 12.3.4 read register 3 (readout of first 48 bits of channel status) ? the first 48 bits of channel status can be read with the demodulation function. ? the readout channel status data is output with lsb first. ? for readout, set the ccb address to 0xec. ? the channel status data cannot be updated after the ccb address is set. ? the relation between the read registers and the channel status data is shown below. table 12.7 read registers of first 48 bits of channel status register bit no. contents register bit no. contents do0 bit 0 application do24 bit 24 sampling frequency do1 bit 1 control do25 bit 25 do2 bit 2 do26 bit 26 do3 bit 3 do27 bit 27 do4 bit 4 do28 bit 28 clock accuracy do5 bit 5 do29 bit 29 do6 bit 6 not defined do30 bit 30 not defined do7 bit 7 do31 bit 31 do8 bit 8 category code do32 bit 32 word length do9 bit 9 do33 bit 33 do10 bit 10 do34 bit 34 do11 bit 11 do35 bit 35 do12 bit 12 do36 bit 36 not defined do13 bit 13 do37 bit 37 do14 bit 14 do38 bit 38 do15 bit 15 do39 bit 39 do16 bit 16 source number do40 bit 40 do17 bit 17 do41 bit 41 do18 bit 18 do42 bit 42 do19 bit 19 do43 bit 43 do20 bit 20 channel number do44 bit 44 do21 bit 21 do45 bit 45 do22 bit 22 do46 bit 46 do23 bit 23 do47 bit 47
LC89057W-VF4A-E no.7202-57/59 12.3.5 read register 4 (burst preamble pc data) ? the burst preamble pc data can be read with the demodulation function. ? the 16 bit-data of burst preamb le pc are output with lsb first. ? for readout, set the ccb address to oxed. ? the relation between the read register and burst preamble pc data is shown below. table 12.8 burst preambl e pc read registers register bit no. contents do0 bit 0 data type do1 bit 1 do2 bit 2 do3 bit 3 do4 bit 4 do5 bit 5 reserved do6 bit 6 do7 bit 7 error do8 bit 8 data type dependent do9 bit 9 information do10 bit 10 do11 bit 11 do12 bit 12 do13 bit 13 bit stream number do14 bit 14 do15 bit 15 12.4 burst preamble pc field ? the burst preamble pc field is shown below. ? for the latest information, re fer to official specifications. table 12.9 burst preamble pc field register value contents do4 to 0 0 null data 1 dolby ac-3 data 2 reserved 3 pause 4 mpeg-1, layer 1 data 5 mpeg-1, layer 2, 3 data, or non-extended mpeg-2 6 extended mpeg-2 data 7 reserved 8 mpeg-2, layer 1, low sampling rate 9 mpeg-2, layer 2, 3, low sampling rate 10 reserved 11 dts type1 12 dts type2 13 dts type3 14 atrac 15 atrack2/3 16 to 26 reserved 27 reserved (mpeg-4, aac data) 28 mpeg-2, aac data 29 to 31 reserved do6, 5 0 reserved (set to "0") do7 0 error flag indicating effective burst payload 1 error flag indicating burst payload error do12 to 8 data type dependent information do15 to 13 0 bit stream number. (set to "0")
LC89057W-VF4A-E no.7202-58/59 13. application example 13.1 basic connection diagram ? connect a de-coupling capacitance (0.1 f) as close as possible to the power s upply pin. use a ceramic capacitor with high-frequency characteristic s for this capacitance. ? use a capacitor with a low temperatur e coefficient for the pll loop filter. table 13.1 recommended circuit parameters ( ?? : see section 10.1.1) element symbol recommended parameter application remarks cc 0.1 f power supply de-coupling ceramic capacitor rp 10k function setting pull-down/pull-up resistor c1 1pf to 33pf quarts resonator load cera mic capacitor with np0 characteristics rf 1m oscillation amplifier feedback rd 220 oscillation amplifier current limit ci 0.1 f coaxial input dc cut ceramic capacitor ri 75 coaxial input termination c0 ?? pll loop filter c1 ?? pll loop filter r0 ?? pll loop filter 21 slrck 22 a din 23 rlrck 24 rdata rerr int ckst a udio/vo 37 do 38 di 39 ce rx0 empha/uo dgnd dv dd x in 40 cl 41 xmode 42 43 dv dd 44 txo/pioen 45 tmck/pio0 rx3 rx1 dgnd dv dd rx6/ui 12 17 rbck 18 dgnd 19 dv dd 20 sbck 46 tbck/pio1 47 48 xout xmck dgnd 14 15 16 13 lpf 11 10 9 8 7 6 5 4 3 2 1 35 36 33 34 31 32 29 30 27 28 25 26 lc89057w-vf4a dgnd rxout rx2 rx4 rx5/vi a v dd a gnd rmck tlrck/pio2 tdata/pio3 dgnd microcontroller microcontroller 24.576mhz / 12.288mhz c0 a /d dsp a /d dsp d/a c1 rf cc cc cc cc cc cc cc chip address setting chip address setting demodulation function master/slave setting modulation/general-purpose i/o function selection rp rp rp rp optical input cl cl r0 coaxial input ri ci * for how to use the rx1, see section 10.2. rd dv dd dv dd
LC89057W-VF4A-E no.7202-59/59 ps this catalog provides information as of november, 2007. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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